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| NBXSBA021, NBXSBB021 3.3 V, 266.667 MHz LVPECL Clock Oscillator The NBXSBB021/NBXSBA021 single frequency crystal oscillator (XO) is designed to meet today's requirements for 3.3 V LVPECL clock generation applications. The device uses a high Q fundamental crystal and Phase Lock Loop (PLL) multiplier to provide 266.667 MHz, ultra low jitter and phase noise LVPECL differential output. This device is a member of ON Semiconductor's PureEdget clock family that provides accurate and precision clock solutions. Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape and reel in quantities of 1,000. Frequency stability options available as either 50 PPM NBXSBA021 or 20 PPM NBXSBB021. Features http://onsemi.com 6 PIN CLCC LN SUFFIX CASE 848AB * * * * * * * * LVPECL Differential Output Uses High Q Fundamental Mode Crystal and PLL Multiplier Ultra Low Jitter and Phase Noise - 0.4 ps (12 kHz - 20 MHz) Output Frequency - 266.667 MHz Hermetically Sealed Ceramic SMD Package RoHS Compliant Operating Range 3.3 V 10% Total Frequency Stability - 20 PPM or 50 PPM MARKING DIAGRAMS NBXSBB021 266.667 AWLYYWW NBXSBA021 266.667 AWLYYWW Applications * Servers * Fully Buffered DIMM NBXSBB021 = NBXSBB021 (20 PPM)* NBXSBA021 = NBXSBA021 (50 PPM) 266.667 = Output Frequency (MHz) A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week ORDERING INFORMATION VDD 6 CLK CLK 54 Device NBXSBB021LN1TAG* NBXSBA021LN1TAG Crystal PLL Clock Multiplier Package CLCC-6 (Pb-Free) CLCC-6 (Pb-Free) Shipping 1000/ Tape & Reel 1000/ Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 3 GND * Please contact sales office for availability 1 OE 2 NC Figure 1. Simplified Logic Diagram (c) Semiconductor Components Industries, LLC, 2008 1 May, 2008 - Rev. 1 Publication Order Number: NBXSBB021/D NBXSBA021, NBXSBB021 OE 1 6 VDD NC 2 5 CLK GND 3 4 CLK Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION Pin No. 1 2 3 4 5 6 Symbol OE NC I/O LVTTL/LVCMOS Control Input N/A Description Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. No Connect. Ground 0 V. AAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAA GND CLK CLK VDD Power Supply LVPECL Output LVPECL Output Power Supply Non-Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD - 2 V. Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to VTT = VDD - 2 V. Positive power supply voltage. Voltage should not exceed 3.3 V 10%. Table 2. OUTPUT ENABLE TRI-STATE FUNCTION OE Pin Open HIGH Level LOW Level Output Pins Active Active High Z Table 3. ATTRIBUTES Characteristic Internal Default State Resistor ESD Protection Human Body Model Machine Model Value 170 kW 2 kV 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol VDD Iout TA Tstg Tsol Parameter Positive Power Supply LVPECL Output Current Operating Temperature Range Storage Temperature Range Wave Solder See Figure 5 Condition 1 GND = 0 V Continuous Surge Condition 2 Rating 4.6 25 50 -40 to +85 -55 to +120 260 Units V mA C C C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 NBXSBA021, NBXSBB021 Table 5. DC CHARACTERISTICS (VDD = 3.3 V 10%, GND = 0 V, TA = -40C to +85C) (Note 2) Symbol IDD VIH VIL IIH IIL VOH VOL VOUTPP Characteristic Power Supply Current (Note 2) OE Input HIGH Voltage OE Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage (Note 2) VDD = 3.3 V Output LOW Voltage (Note 2) VDD = 3.3 V Output Voltage Amplitude (Note 2) OE OE 2000 GND - 300 -100 -100 VDD-1195 2105 VDD-1945 1355 700 Conditions Min. Typ. 75 Max. 100 VDD 800 +100 +100 VDD-945 2355 VDD-1600 1700 Units mA mV mV mA mA mV mV mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Measurement taken with outputs terminated with 50 ohm to VDD-2 V. See Figure 4. http://onsemi.com 3 NBXSBA021, NBXSBB021 Table 6. AC CHARACTERISTICS (VDD = 3.3 V 10%, GND = 0 V, TA = -40C to +85C) (Note 3) Symbol fCLKOUT Df Characteristic Output Clock Frequency Frequency Stability - NBXSBB021 Frequency Stability - NBXSBA021 Phase-Noise Performance fCLKout = 266.667 MHz 0C to +70C -40C to +85C (Note 4) 100 Hz of Carrier 1 kHz of Carrier 10 kHz of Carrier 100 kHz of Carrier 1 MHz of Carrier 10 MHz of Carrier tjit(F) tjitter RMS Phase Jitter Cycle to Cycle, RMS Cycle to Cycle, Peak-to-Peak Period, RMS Period, Peak-to-Peak tOE/OD tDUTY_CYCLE tR tF tstart Output Enable/Disable Time Output Clock Duty Cycle (Measured at Cross Point) Output Rise Time (20% and 80%) Output Fall Time (80% and 20%) Start-up Time Aging 1st Year 1st 48 50 250 250 1 12 kHz to 20 MHz 1000 Cycles 1000 Cycles 10,000 Cycles 10,000 Cycles -102 -114 -123 -123 -132 -157 0.4 1.5 10 1 7 0.9 8 30 4 20 200 52 400 400 5 3 1 Conditions Min. Typ. 266.667 20 50 Max. Units MHz PPM FNOISE dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps ps ps ps ps ns % ps ps ms ppm ppm Every Year After NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Measurement taken with outputs terminated with 50 ohm to VDD-2 V. See Figure 4. 4. Parameter guarantees 10 years of aging. Includes initial stability at 25C, shock, vibration, and first year aging. Figure 3. Typical Phase Noise Plot http://onsemi.com 4 NBXSBA021, NBXSBB021 Table 7. RELIABILITY COMPLIANCE Parameter Shock Mechanical Mechanical Mechanical Mechanical Standard Method MIL-STD-833, Method 2002, Condition B MIL-STD-833, Method 2003 AAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A Solderability Vibration MIL-STD-833, Method 2007, Condition A MIL-STD-202, Method 215 Solvent Resistance Thermal Shock Environment Environment MIL-STD-833, Method 1011, Condition A Moisture Level Sensitivity MSL1 260C per IPC/JEDEC J-STD-020D NBXSBB021/NBXSBA021 CLK Driver Device CLK Zo = 50 W 50 W 50 W VTT VTT = VDD - 2.0 V D Zo = 50 W D Receiver Device Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) Temperature (C) 260 217 temp. 260C 20 - 40 sec. max. peak 3C/sec. max. 6C/sec. max. ramp-up 175 150 cooling pre-heat reflow Time 60180 sec. 60150 sec. Figure 5. Recommended Reflow Soldering Profile http://onsemi.com 5 NBXSBA021, NBXSBB021 PACKAGE DIMENSIONS 6 PIN CLCC, 7x5, 2.54P CASE 848AB-01 ISSUE C D D1 A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. DIM A A1 A2 A3 b D D1 D2 D3 E E1 E2 E3 e L R SEATING PLANE MIN 1.70 MILLIMETERS NOM MAX 1.80 1.90 0.70 REF 0.36 REF 0.10 0.12 1.40 1.50 7.00 BSC 6.20 6.23 6.81 6.96 5.08 BSC 5.00 BSC 4.40 4.43 4.80 4.95 3.49 BSC 2.54 BSC 1.27 1.37 0.70 REF 4X 0.15 C TERMINAL 1 INDICATOR E2 H E1 E 0.08 1.30 6.17 6.66 D2 TOP VIEW A3 0.10 C A A1 SIDE VIEW C D3 e 1 2 3 A2 4.37 4.65 1.17 SOLDERING FOOTPRINT* R E3 0.10 C A B 0.05 C 6X 6X 1.50 5.06 6 5 4 6X b BOTTOM VIEW L 2.54 PITCH 6X 1.50 DIMENSION: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 6 NBXSBB021/D |
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